Research Seminar by Dr. Antonio Portero.

Title: “A co-design approach for memory subsystem performance analysis in HPC"

Presenter: Dr. Antonio Portero

Dr Antoni Portero Trujillo (Male) received his PhD in Computer Science (Summa Cum Laude), his master's in microelectronics, and his bachelor's in electronic engineering, all from the University of Autónoma of Barcelona. He joined Jülich Supercomputing Centre in 2019. He is a research scientist in the Next Generation Architectures and Prototypes Group; his current works are involved in research activities in the EPI (European Processor Initiative) project. Previously, he was a senior researcher at IT4I National Supercomputing Centre in the Czech Republic (2013-2019). He was also a visiting researcher at the Politecnico di Milano (2015), a research associate at the University of Siena (2009-2013) and an international student at IMEC (2001). In addition, he worked on several EU H2020 and FP7 projects, HARPA (Harnessing Performance Variability), Teraflux (Exploiting Dataflow Parallelism in Teradevice Computing), and ERA (Embedded Reconfigurable Architectures) and national-funded projects. He is interested in large-scale hardware architectures for the exascale and exaflop operations, HW/SW codesign of High-Performance Systems, focusing on chip design, Heterogeneous architectures and modular design. He is a member of HiPEAC (High-Performance Embedded-system Architecture and Compiler) and a senior IEEE and ACM member.

Place: Seminari de Microelectrònica, Friday 7th of July by 9:00AM